1. Field of the Invention
This invention relates to the production of integrated circuit structures on a semiconductor substrate. More particularly it relates to the use of one or more silicon layers in the formation of defect-free source/drain regions, by implantation and out-diffusion of the one or more silicon layers into the substrate, and later formation of silicon nitride spacers from the one or more silicon layers.
2. Description of the Related Art
As geometries of integrated circuit structures have been reduced, the contribution of defects in a single crystal silicon semiconductor substrate, created during implantation of the substrate to form source/drain regions of an MOS device, gains in importance because such implant-caused crystal defects in a single crystal semiconductor substrate, such as a single crystal silicon substrate, adversely affect the subsequent dopant diffusion in the lightly doped drain (LDD) or heavily doped drain (HDD), and into channel regions of such an MOS device formed in the substrate.
While it is known to implant a sacrificial diffusion layer on a single crystal semiconductor substrate followed by out-diffusion of the dopant from the diffusion layer into the substrate to thereby isolate the implantation-generated defects from the substrate, some manner of protection must be afforded to the channel region of the substrate under the gate electrode during concurrent implantation of a polysilicon gate electrode and then diffusion of the dopant into and through the gate electrode during annealing to concurrently form the source/drain regions in the substrate. This is a particular problem since such dopants may diffuse at a faster rate through the polysilicon gate electrode (toward the underlying channel region) than the dopants diffusing into the single crystal semiconductor deep enough to form the desired source/drain regions.
Pending Aronowitz et al. U.S. patent application Ser. No. 08/816,254, filed by one of us on Mar. 13, 1997, and assigned to the assignee of this invention, the disclosure of which is hereby incorporated by reference, discusses the problems of protecting the underlying channel area of a semiconductor substrate during doping of the gate electrode. The above-referenced Aronowitz et al. patent application suggests and claims the formation of a nitridized silicon barrier layer over the gate oxide and beneath the polysilicon gate electrode by the treating, with a nitrogen plasma, of a thin layer of silicon formed over the gate oxide to thereby form a nitridized silicon dopant barrier layer. This nitridized silicon layer then prevents penetration of the gate electrode dopant through the barrier layer into the gate oxide, and the channel region of the substrate beneath the gate oxide during the annealing step.
While the above-referenced Aronowitz et al. patent application addresses the problem of dopant diffusion into the channel region of a single crystal substrate below the gate electrode, the use of an implant and out-diffusion layer over the substrate and the gate electrode still introduces additional process steps in the formation and subsequent removal of such a layer. While it has been proposed to subsequently use such an implant and out-diffusion layer (when the layer comprises silicon) in the formation of metal silicide contacts, this is not always useful or desirable, thus necessitating removal of the implant and out-diffusion layer after formation of the source/drain regions, which adds to the complexity and expense of the process.
It would be desirable if the problem of implant-caused defects in the substrate could be rectified by the use of an implantation and outdiffusion layer over the substrate which layer could not only be used in the formation of source/drain regions of varying dopant density, but then further used in the formation of a desired component of the integrated circuit structure, other than a metal silicide contact.